Problem 6: Static Timing Verification
- Q1:測試檔二,三的結果好像有問題 (April 16, 2000).
- A1:Sorry for the mistakes! We have corrected the errors.
Please download the new set of test cases and their sample results
(April 19, 2000).
- Q2: Will a FSM exist in the test program? That is, whether the
DFFs can be located in the middle of the ckt or DFFs can just be used only
for latching the input or output. (April 20, 2000)
- A2:Please consider only the Moore machine.
DFFs are used only for inputs and outputs. (April 28, 2000)
- Q3: Could those outputs in the netlist be
(1) all are latched by DFF,
(2) none is latched by DFF, or
(3) some are latched by DFF but others are not.
- A3:測試電路將會是以下兩種類型
1. 完全沒有latch(DFF)，如範例1, 3
2. output 端全部以latch(DFF)做輸出，如範例 2
- Q4: (1). 題目所給的LIBRARY是大寫的，
我們是否需要將大小寫列入考慮？亦或是根據題目H
(2). 題目上面說可以做FALSE PATH 的功能，請問一下該如何做驗證？
(3). 題目上有兩個constraints 不知道是不是只有這兩個限制而已，
還是有其他限制‥ 限制又是如何？
(4). 題目所給的第二個限制 Create_clock -period 10 -name clk1
其中對於period
還是將他設成 high 5 ns and low 5ns (no sl功能ew)？
- A4:(1). 測試電路將完全依照範例的類型,
(2). 測試結果將依照 synopsys 的輸出為標準,
(3), (4). 只會有這兩個constraint，但時間值可能會變，
如 set_max_delay 5 -to all_outpu)
For any questions, send e-mails to cad@cis.nctu.edu.tw.
Last modified: April 19, 2000