Problem 5: IP Timing Characterization
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Q1: [2001/03/19]
請問有關第五題的input netlist 是很單純的 nand, nor gates , etc. 嗎?
還是會有supercell 裡面包含一些基本 gates 兜成的線路, like MUX ?
A1: [2001/03/22]
All gates that will be used for test are listed in the *.lib file. So please don't worry about other gates.
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Q2: [2001/05/09]
I found that the two given circuits have only sequential components.
And, I wonder if another circuit of sequauential and combinational
mixed can be given for the reason of verification !?
A2: [2001/05/17]
We will test your program based only onsequential components, like the posted testcases.
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Q3: [2001/05/30]
關於recovery time ，在給定的 library 中，有關 preset 與 clear 的 lookup table 只有 rising
但是在第二個測試檔中的 model data file，brt_clk 的recovery time 卻有 rising 跟 falling 的結果。
那我們想請教的是，lookup table只有rising 可是 fall 的recovery time 要怎麼lookup呢 ?
pin(SN) {
direction : input;
capacitance : 0.01098;
min_pulse_width_low : 0.8100;
timing() {
related_pin : "CK";
timing_type : recovery_rising;
rise_constraint(recovery_template_3x2) {
index_1 ("0.0500, 0.9000, 3.0000");
index_2 ("0.0500, 3.0000");
values ( \
"-0.0078, -0.0312", \
"0.0156, -0.0156", \
"0.0469, -0.0156");
}
}
}
pin(RN) {
direction : input;
capacitance : 0.00392;
min_pulse_width_low : 0.8100;
timing() {
related_pin : "CK";
timing_type : recovery_rising;
rise_constraint(recovery_template_3x2) {
index_1 ("0.0500, 0.9000, 3.0000");
index_2 ("0.0500, 3.0000");
values ( \
"0.2031, 0.1406", \
"0.2656, 0.2031", \
"0.2344, 0.1641");
}
}
}
A3: [2001/06/01]
Here are the answers provided by Global Unichip.
In example 6 of problem 5 shown in page 9, the model of recovery time was
defined as follows.
/* The recovery time of Preset with respect to positive edge CLK. */
Preset_CLK :
RECOVERY (POSEDGE) Preset CLK ;
where POSEDGE means positive clock edge CLK, and there are no declarations of check edge for Preset.
This model implies that both of rising Preset and falling Preset must be considered.
In other words, the above model is the combination of the following two models.
Preset_CLK :
RECOVERY (POSEDGE, POSEDGE) Preset CLK ;
Preset_CLK_1 :
RECOVERY (NEGEDGE, POSEDGE) Preset CLK ;
In general, the present (reset) signal of a Flip-Flop is either active HIGH or active LOW.
If it is active High, one should use falling preset (reset) with respect to rising CLK to model
the recovery time. Otherwise, one should use rising preset (reset) with repect to rising CLK
to model the recovery time. In the above example, if Preset is active HIGH(LOW), Preset_CLK_1
(Preset_CLK ) is used to model the recovery time with respect to positive edge CLK.
In the synopsys model (problem5.lib) we delivered, both of the preset (SN) and reset (RN)
pins are active LOW. Therefore, only rising recovery time LUT is provided.
In short, the students only need to provide the rising recovery time for brt_clk as below.
brt_clk :
RECOVERY (POSEDGE, POSEDGE) brt clk ;
Similarly, only rising recovery time is characterized for preset or reset signals for other testcases.
For any questions, send e-mails to cad@cis.nctu.edu.tw.
Last modified: June 2, 2001