Problem 6: Clock Tree Synthesis

Problem 6: Clock Tree Synthesis

Q1: [2001/03/16]
有關timing library file的使用方法是否能舉個例子加以說明，當我有total fanout capacitances and input slop of the buffer 這些相關資料後，我如何用該檔案找出所要的delay and output slop of the buffer.

A1: [2001/03/28]
Assume that the output capacitance and input slope of a cell have been calculated. Also, let the cell be mapped to the library cell BUF1CK. If you want to find the rise delay, you need to do the following.
- Step 1. Find out the the Model for the cell BUF1CK. There is a name called "rise_x1MOd" in the table.
  
  Model(ioDelayRiseModel0 rise_x1Mod
  (Spline
  data(
  (0.112600 0.127000 0.154600 0.209200 0.317100 0.963900)
  (0.125000 0.139500 0.167100 0.221400 0.329300 0.976000)
  (0.150900 0.165500 0.192900 0.246700 0.354400 1.000900)
  (0.189300 0.204200 0.231900 0.285400 0.392200 1.038000)
  (0.241200 0.256800 0.285500 0.339500 0.446300 1.090600)
  (0.309200 0.325900 0.356300 0.412000 0.520300 1.165700)
  )
  )
  )
- Step 2. Find another table called rise_x1Mod shown below.
  This table shows both the input slew and the load axis.
  
  Model(rise_x1Mod
  (Spline
  (Input_Slew_Axis 0.094500 0.178300 0.331200 0.625500 1.1871002.173400)
  (Load_Axis 0.008400 0.016400 0.032400 0.064400 0.128400 0.512400)
  data()
  )
  )
- Step 3. For example, if the (input slope, total capacitance's) = (0.094500, 0.032400). Referring to the rise_X1Mod table, you can find that 0.0945 corresponds to the first entry and 0.0324 corresponds to the third entry in the table. Then, looking up the table shown in Step 1, the entry in the first row and the third column gives the value 0.154600, which is the rise delay.
- Step 4. Similarly, you can find the output slew in the same way by looking up the table for slew.
- Step 5. If the input slew or the output capacitance is not exactly the same as the values listed in the table mentioned in Step 2. Use interpolation to estimate the value.
Q2: [2001/03/16]
對buffer size所做的改變要如何在輸出檔中表示呢？有關buffer size 題目所給資料也沒說清楚，難道每個buffer的大小都一樣嗎？那我到底要對buffer做什麼改變（大小或數目或是什麼），以達到題目的要求呢？希望能予以解釋。

A2: [2001/03/28]
The objective of this problem is to find the best library cell for each buffer so that the clock skew is under some constraint and the clock delay is minimized. Listed in the library, there are several buffers of different sizes. Each library (buffer) cell has a different driving strength, resulting in different arrival times of clock pins. The input to the problem is a text file describing the clock tree where each buffer in the clock tree has already been mapped to some library cell. The goal is to find the "best" library (buffer) cell for each buffer in the clock tree so that the skew is under some constraint and the clock delay is minimized.
Q3: [2001/03/29]
在 benchmarks 中，命名並不一致
例如 p6-2.ct line1 ARMDMI_NEW/LCLK_L1_I1
p6-2.rspf line150 ARMDMI_NEW|LCLK_L1_I1
ct 檔用 '/' 而 rspf 檔用 '|' 請問我們該以那個命名法做標準？

A3: [2001/04/12]
Faraday has made the format the same. The new test files are available on-line now.
Q4: [2001/05/02]
在timing library中，每一cell後面，都有一項Timing_Props(Load_Limit(...))。請問在進行buffer selection時，是否需要考慮此限制？
例如：BUF1CK的Load_Limit為0.3024，若某一 cell的負載大於0.3024，則該cell便不能選用BUF1CK為其buffer，僅能考慮其它buffer，對或不對？

A4: [2001/05/09]
Yes, you are quite right. We have to consider the load limit.

For any questions, send e-mails to cad@cis.nctu.edu.tw.

Last modified: May 10, 2001