Each test case requires using the following 
four files:
(1) p6-constraint.in (apply to all test cases):
    description of the clock-skew constraint.
(2) p6-*.ct (specific to each individual test
    case): 
    simplified clock-tree description
    (Note that the contest committee has 
    decided to simplify the original Verilog
    format to the current format so that you
    don't need to write any parser for a 
    Verilog code.)
(3) p6-*.rspf (specific to each individual test
    case): 
    description of clock-tree parasitics.
(4) p6-timing.tlf (apply to all test cases):
    The timing library of buffers. We will use
    this library for all test cases. Therefore,
    you may simply copy the library into your
    code. Hopefully, this simplification can
    significantly reduce the complexity of this
    problem.