Problem 8: Pattern Generator for Built-In Self-Test
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Q1: [2001/05/24]
1.請問如何由所提供的verilog測試檔中取得scan path的長度與數目？
這兩個值會影響PRPG的設計，因此希望能知道如何從所提供的verilog得知這兩個值。
（另外，如果可以，可否提供Verilog parser的程式，和它的使用方法與輸出格式）
2.關於輸出的patterns所用的VCD格式，可否加以說明並舉例。PRPG的verilog形式是否有所
規定，像是輸入輸出接腳的格式等。
A1: [2001/05/29]
Please see A1 and A2 for the answers from SynTest.
A1. Actually one has to analyze the circuit and find it out.
Nevertheless, here are the report files containing the
scan-chain information of the three designs.
1. circuit p8_1.v
======================================================
Number of Scan chain = 1
======================================================
Scan chain 1 :
Scan instance file name: ./sel/uart.sel1.pso
Scan instance number = 24
Scan CLOCK = +clk.
Synchronous CLOCK = +clk.
======================================================
Memory elements : 24
Scan elements : 24
Delay elements : 0
Transparent latch : 0
2. circuit p8_2.v
======================================================
Number of Scan chain = 2
======================================================
Scan chain 1 :
Scan instance file name: ./sel/system.sel1.pso
Scan instance number = 578
Scan CLOCK = +clk.
Synchronous CLOCK = +clk.
--------------------------------------------------
Scan chain 2 :
Scan instance file name: ./sel/system.sel2.pso
Scan instance number = 72
Scan CLOCK = -clk.
Synchronous CLOCK = -clk.
======================================================
Memory elements : 4563
Scan elements : 650
Delay elements : 0
Transparent latch : 3913
3. circuit p8_3.v
======================================================
Number of Scan chain = 2
======================================================
Scan chain 1 :
Scan instance file name: ./sel/IDCT.sel1.pso
Scan instance number = 522
Scan CLOCK = +clk.
Synchronous CLOCK = +clk.
--------------------------------------------------
Scan chain 2 :
Scan instance file name: ./sel/IDCT.sel2.pso
Scan instance number = 1537
Scan CLOCK = -clk.
Synchronous CLOCK = -clk.
======================================================
Memory elements : 2700
Scan elements : 2059
Delay elements : 0
Transparent latch : 640
A2. No, as long as you can simulate it.
For any questions, send e-mails to cad@cis.nctu.edu.tw.
Last modified: May 30, 2001