module test;
reg         CLK, Reset;
reg  [31:0] DataIn, InsIn;
reg  [31:0] Imem[0:32767], Dmem[0:32767];
wire [31:0] IAddr, DAddr, DataOut;
integer count;

PCPU cpu(CLK,Reset,DataIn,InsIn,IAddr,DAddr,DataOut,WEmem);

always #15 CLK=~CLK;

// read function for Data Memory and Instruction Memory
always @(DAddr) DataIn=Dmem[DAddr];
always @(IAddr) InsIn=Imem[IAddr];

// write function for Data Memory
always @(posedge CLK) begin
   if (WEmem) Dmem[DAddr]=DataOut;
end

always @(posedge CLK) begin
   if ((!Reset)&&(cpu.CU.stallIF)) begin
      if (cpu.CU.stall2) count=count-1;
      else count=count+1;
   end
end

initial begin
   count=0; CLK=0; Reset=1;
   $readmemb("cputest.pro",Imem,0,32767); // load test program
   #20 Reset=0;
   #1000000;
   $display("\nInstructions executed:%d  Clock cycle used:%d\n",count-3,
           ($time-5)/30);
   $finish;
end
endmodule


// The core of the pipelined CPU

module PCPU(CLK,Reset,DataIn,InsIn,IAddr,DAddr,DataOut,WEmem);

input        CLK, Reset;
input[31:0]  DataIn, InsIn;
output       WEmem;
output[31:0] IAddr, DAddr, DataOut;

wire[31:0]   InsIn, DataIn, DataOut, IAddr, DAddr;
wire[15:0]   Imme16;
wire[4:0]    RAddr1, RAddr2, RAddr3, WAddr;
wire[2:0]    ALUop, MuxPC;
wire[1:0]    MuxA1, MuxA2, MuxD;
wire         cond, PCop, MuxR, WEcond, WEbuf1, WEbuf2, WEregf, WEomdr;
wire         OEregf, OErb, WEtemp, OEtemp, WEPC, WEimar, WEdmar, WEimdr;

controller   CU(CLK, Reset, InsIn, cond, MuxA1, MuxA2, ALUop, MuxPC, PCop,
                MuxD, MuxR, WEcond, WEbuf1, WEbuf2, WEregf, OEregf, OErb,
                WEtemp, OEtemp, WEPC, WEimar, WEdmar, WEimdr, WEomdr,
                RAddr1, RAddr2, RAddr3, WAddr, Imme16, WEmem);
datapath     DA(CLK, Reset, MuxA1, MuxA2, ALUop, MuxPC, PCop, MuxD, MuxR,
                WEcond, WEbuf1, WEbuf2, WEregf, OEregf, OErb, WEtemp, OEtemp,
                WEPC, WEimar, WEdmar, WEimdr, WEomdr, RAddr1, RAddr2, RAddr3,
                WAddr, Imme16, DataIn, IAddr, DAddr, DataOut, cond);
endmodule


module controller(CLK, Reset, InsIn, cond, MuxA1, MuxA2, ALUop, MuxPC, PCop,
                  MuxD, MuxR, WEcond, WEbuf1, WEbuf2, WEregf, OEregf, OErb,
                  WEtemp, OEtemp, WEPC, WEimar, WEdmar, WEimdr, WEomdr,
                  RAddr1, RAddr2, RAddr3, WAddr, Imme16, WEmem);

input[31:0]  InsIn;
input        CLK, Reset, cond;
output[15:0] Imme16;
output[4:0]  RAddr1, RAddr2, RAddr3, WAddr;
output[2:0]  ALUop, MuxPC;
output[1:0]  MuxA1, MuxA2, MuxD;
output       PCop, MuxR, WEcond, WEbuf1, WEbuf2, WEregf, OEregf;
output       OErb, WEtemp, OEtemp, WEPC, WEimar, WEdmar, WEimdr, WEomdr, WEmem;

wire[31:0]   IR1Out, IR2Out, IR3Out, IR4Out;
wire[2:0]    MuxPC1;
wire         WEir1, WEir2, WEir3, WEir4, stall1, stall2, halt;
wire         stallIF, stallID, stallEXE, stallMEM, stallWB;
wire         iWEcond,iWEdmar,iWEomdr,iWEimdr,iWEmem,iWEregf;

Reg32_NCK    IR1(CLK,Reset,WEir1,InsIn,IR1Out);
Reg32_NCK    IR2(CLK,Reset,WEir2,IR1Out,IR2Out);
Reg32_NCK    IR3(CLK,Reset,WEir3,IR2Out,IR3Out);
Reg32_NCK    IR4(CLK,Reset,WEir4,IR3Out,IR4Out);
assign Imme16=IR1Out[15:0];
assign RAddr1=IR1Out[20:16];
assign RAddr2=IR1Out[15:11];
assign RAddr3=IR1Out[25:21];
assign WAddr=IR4Out[25:21];
assign WEPC=stallIF;
assign WEimar=stallIF;
assign OEregf=stallID;
assign WEtemp=stallID;
assign WEbuf1=stallEXE;
assign WEbuf2=stallMEM;

assign WEir1=stallIF;
assign WEir2=stallID;
assign WEir3=stallEXE;
assign WEir4=stallMEM;

DecodeEXE    dec1(IR2Out[31:26],cond,ALUop,MuxPC1,PCop,iWEcond,OErb,OEtemp,
                  iWEdmar,iWEomdr,stall2);
DecodeMEM    dec2(IR3Out[31:26],iWEimdr,iWEmem);
DecodeWB     dec3(IR4Out[31:26],MuxR,iWEregf,halt);

Forward      for1(IR2Out[31:11],IR3Out[31:11],IR4Out[31:11],MuxPC1,MuxA1,MuxA2,
                  MuxPC,MuxD,stall1);

Stall        stl(CLK,Reset,stall1,stall2,halt,stallIF,stallID,stallEXE,
                 stallMEM,stallWB);
SEXE         stl1(stallEXE,iWEcond,iWEdmar,iWEomdr,WEcond,WEdmar,WEomdr);
SMEM         stl2(stallMEM,iWEimdr,iWEmem,WEimdr,WEmem);
SWB          stl3(stallWB,iWEregf,WEregf);
endmodule


module Reg32_NCK(CLK,Reset,WE,DIn,DOut);

input[31:0]  DIn;
input        CLK, Reset, WE;
output[31:0] DOut;
wire[31:0]   DIn;
reg[31:0]    DOut;

always @(negedge CLK) begin
   if (Reset) DOut=0;
   else begin
      if (WE) DOut=DIn;
//      else DOut=DOut;
   end
end
endmodule


module Reg4_NCK(CLK,Reset,WE,DIn,DOut);

input[3:0]   DIn;
input        CLK, Reset, WE;
output[3:0]  DOut;
wire[3:0]    DIn;
reg[3:0]     DOut;

always @(negedge CLK) begin
   if (Reset) DOut=0;
   else begin
      if (WE) DOut=DIn;
//      else DOut=DOut;
   end
end
endmodule


module DecodeEXE(op,cond,ALUop,MuxPC,PCop,WEcond,OErb,OEtemp,WEdmar,WEomdr,
                 stall2);

input[5:0]   op;
input        cond;
output[2:0]  ALUop, MuxPC;
output       PCop, WEcond, OErb, OEtemp, WEdmar, WEomdr, stall2;
reg[2:0]     ALUop, MuxPC;
reg          PCop, WEcond, OEselect, WEdmar, WEomdr, stall2;

assign OErb=~OEselect;
assign OEtemp=OEselect;

always @(op or cond) begin
   ALUop=0; MuxPC=0; PCop=0; WEcond=0; OEselect=0; WEdmar=0; WEomdr=0;
   stall2=0;
   case(op[5:3])
      3'b000: begin   // Data Transfer
         case(op[2:0])
            3'b000: begin   // LD
               ALUop=1; WEdmar=1;
            end
            3'b001: begin   // LDI
               ALUop=1; OEselect=1; WEdmar=1;
            end
            3'b010: begin   // ST
               ALUop=1; WEdmar=1; WEomdr=1;
            end
            3'b011: begin   // STI
               ALUop=1; OEselect=1; WEdmar=1; WEomdr=1;
            end
            3'b100: begin   // MOV
               OEselect=0;
            end
            3'b101: begin   // MOVI
               OEselect=1;
            end
         endcase
      end
      3'b001: begin   // Arithmetic Operation
         case(op[2:0])
            3'b000: begin   // ADD
               ALUop=1; 
            end
            3'b001: begin   // SUB
               ALUop=2;
            end
            3'b100: begin   // ADDI
               ALUop=1; OEselect=1;
            end
            3'b101: begin   // SUBI
               ALUop=2; OEselect=1;
            end
         endcase
      end
      3'b010: begin   // Compare to register
         case(op[2:0])
            3'b000: begin   // SLT
               ALUop=3; WEcond=1;
            end
            3'b001: begin   // SGT
               ALUop=4; WEcond=1;
            end
            3'b010: begin   // SLE
               ALUop=5; WEcond=1;
            end
            3'b011: begin   // SGE
               ALUop=6; WEcond=1;
            end
            3'b100: begin   // SEQ
               ALUop=7; WEcond=1;
            end
         endcase
      end
      3'b011: begin   // Compare to immediate
         case(op[2:0])
            3'b000: begin   // SLTI
               ALUop=3; OEselect=1; WEcond=1;
            end
            3'b001: begin   // SGTI
               ALUop=4; OEselect=1; WEcond=1;
            end
            3'b010: begin   // SLEI
               ALUop=5; OEselect=1; WEcond=1;
            end
            3'b011: begin   // SGEI
               ALUop=6; OEselect=1; WEcond=1;
            end
            3'b100: begin   // SEQI
               ALUop=7; OEselect=1; WEcond=1;
            end
         endcase
      end
      3'b100: begin   // Branch and Jump
         case(op[2:0])
            3'b000: begin   // BRT
               if (cond) begin
                  PCop=1; stall2=1;
               end
            end
            3'b001: begin   // BRF
               if (!cond) begin
                  PCop=1; stall2=1;
               end
            end
            3'b010: begin   // BRTI
               if (cond) begin
                  PCop=1; MuxPC=4; stall2=1;
               end
            end
            3'b011: begin   // BRFI
               if (!cond) begin
                  PCop=1; MuxPC=4; stall2=1;
               end
            end
            3'b100: begin   // JMP
               PCop=1; stall2=1;
            end
            3'b101: begin   // JMPI
               PCop=1; MuxPC=4; stall2=1;
            end
         endcase
      end
   endcase
end
endmodule


module DecodeMEM(op,WEimdr,WEmem);

input[5:0]   op;
output       WEimdr, WEmem;
reg          WEimdr, WEmem;

always @(op) begin
   WEimdr=0; WEmem=0;
   if (op[5:2]==4'b0000) begin
      case(op[1])
         1'b0: WEimdr=1;   // LD or LDI
         1'b1: WEmem=1;    // ST or STI
      endcase
   end
end
endmodule


module DecodeWB(op,MuxR,WEregf,halt);

input[5:0]   op;
output       MuxR, WEregf, halt;
reg          MuxR, WEregf, halt;

always @(op) begin
   MuxR=0; WEregf=0; halt=0;
   if (op[5:4]==2'b00) begin
      if (op[3:2]==2'b00) begin
         if (!op[1]) WEregf=1;   // LD or LDI
      end
      else begin
         WEregf=1; MuxR=1;
      end
   end
   if (op==6'b111111) halt=1;
end
endmodule


module Forward(op1,op2,op3,MuxPCin,MuxA1,MuxA2,MuxPCout,MuxD,stall1);

input[20:0]  op1, op2, op3;
input[2:0]   MuxPCin;
output[2:0]  MuxPCout;
output[1:0]  MuxA1, MuxA2, MuxD;
output       stall1;
reg[2:0]     MuxPCout;
reg[1:0]     MuxA1, MuxA2, MuxD;
reg          stall1;

wire[1:0]    ans1, ans2, ans5;
wire         ans3, ans4;

TABLE1       t1(op2[20:15],ans1);
TABLE1       t2(op3[20:15],ans2);
TABLE2       t3(op1[20:15],ans3);
TABLE3       t4(op1[20:15],ans4);
TABLE4       t5(op1[20:15],ans5);

always @(op1 or op2 or op3 or MuxPCin or ans1 or ans2 or ans3 or ans4 or ans5)
begin
   MuxA1=0; MuxA2=0; MuxPCout=MuxPCin; MuxD=0; stall1=0;
   // Source3==Destination1
   if ((op1[14:10]==op2[14:10])&&(ans1[0])&&(ans5[0])) begin
      case(ans1[1])
         1'b0: begin
            if (ans5[1]) MuxD=1;
            else MuxPCout=1;
         end
         1'b1: stall1=1;
      endcase
   end
   // Source1==Destination1
   if ((op1[9:5]==op2[14:10])&&(ans1[0])&&(ans3)) begin
      case(ans1[1])
         1'b0: MuxA1=1;
         1'b1: stall1=1;
      endcase
   end
   // Source2==Destination1
   if ((op1[4:0]==op2[14:10])&&(ans1[0])&&(ans4)) begin
      case(ans1[1])
         1'b0: MuxA2=1;
         1'b1: stall1=1;
      endcase
   end
   // Source3==Destination2
   if ((op1[14:10]==op3[14:10])&&(ans2[0])&&(ans5[0])) begin
      case(ans2[1])
         1'b0: begin
            if (ans5[1]) MuxD=2;
            else MuxPCout=2;
         end
         1'b1: begin
            if (ans5[1]) MuxD=3;
            else MuxPCout=3;
         end
      endcase
   end
   // Source1==Destination2
   if ((op1[9:5]==op3[14:10])&&(ans2[0])&&(ans3)) begin
      case(ans2[1])
         1'b0: MuxA1=2;
         1'b1: MuxA1=3;
      endcase
   end
   // Source2==Destination2
   if ((op1[4:0]==op3[14:10])&&(ans2[0])&&(ans4)) begin
      case(ans2[1])
         1'b0: MuxA2=2;
         1'b1: MuxA2=3;
      endcase
   end
end
endmodule


module TABLE1(op,yesno);   // For Destination

input[5:0]   op;
output[1:0]  yesno;
reg[1:0]     yesno;

always @(op) begin
   yesno=0;
   if (op[5:4]==2'b00) begin
      if (op[3]) yesno=1;     // ALU
      else begin
         case(op[2:1])
            2'b00: yesno=3;   // LD
            2'b10: yesno=1;   // MOV
         endcase
      end
   end
end
endmodule


module TABLE2(op,yesno);   // For Source 1

input[5:0]   op;
output       yesno;
reg          yesno;

always @(op) begin
   yesno=0;
   if (!op[5]) begin
      if (op[4]) yesno=1;
      else begin
         case(op[3:2])
            2'b00: yesno=1;   // LD or ST
            2'b10: yesno=1;   // ALU
            2'b11: yesno=1;   // ALU with immediate
         endcase
      end
   end
end
endmodule


module TABLE3(op,yesno);   // For Source 2

input[5:0]   op;
output       yesno;
reg          yesno;

always @(op) begin
   yesno=0;
   if (!op[5]) begin
      case(op[4:3])
         2'b00: begin
            if (!op[0]) yesno=1;
         end
         2'b01: begin
            if (!op[2]) yesno=1;
         end
         2'b10: yesno=1;
      endcase
   end
end
endmodule


module TABLE4(op,yesno);   // For Source 3

input[5:0]   op;
output[1:0]  yesno;
reg[1:0]     yesno;

always @(op) begin
   yesno=0;
   if (op[4:3]==2'b00) begin
      if (op[5]) begin
         if (op[2]) begin
            if (op[1:0]==2'b00) yesno=1;
         end
         else begin
            if (!op[1]) yesno=1;
         end
      end
      else begin
         if (op[2:1]==2'b01) yesno=3;
      end
   end
end
endmodule


module Stall(CLK,Reset,stall1,stall2,halt,stallIF,stallID,stallEXE,stallMEM,
             stallWB);

input        CLK, Reset, stall1, stall2, halt;
output       stallIF, stallID, stallEXE, stallMEM, stallWB;
reg          stallIF, stallID, stallEXE, stallMEM, stallWB;
supply1      Enable;

reg          SF, SD, SE, SM, SW;
wire[3:0]    Cstate;
reg[3:0]     Nstate;

`define S0 4'b0000
`define S1 4'b0001
`define S2 4'b0010
`define S3 4'b0011
`define S4 4'b0100
`define S5 4'b0101
`define S6 4'b0110
`define S7 4'b0111
`define S8 4'b1000
`define S9 4'b1001
 
Reg4_NCK     state(CLK,Reset,Enable,Nstate,Cstate);

always @(Reset or stall1 or stall2 or Cstate) begin
   case(Cstate)
      `S0: Nstate=`S1;
      `S1: Nstate=`S2;
      `S2: begin
         if (stall1) Nstate=`S4;
         else if (stall2) Nstate=`S6;
         else Nstate=`S3;
      end
      `S3: Nstate=`S7;
      `S4: Nstate=`S5;
      `S5: Nstate=`S3;
      `S6: Nstate=`S1;
      `S7: begin
         if (stall1) Nstate=`S8;
         else if (stall2) Nstate=`S9;
         else Nstate=`S7;
      end
      `S8: Nstate=`S5;
      `S9: Nstate=`S1;
      default: Nstate=`S0;
   endcase
end

always @(Cstate) begin
   case(Cstate)
      `S0: begin
         SF=1; SD=0; SE=0; SM=0; SW=0;
      end
      `S1: begin
         SF=1; SD=1; SE=0; SM=0; SW=0;
      end
      `S2: begin
         SF=1; SD=1; SE=1; SM=0; SW=0;
      end
      `S3: begin
         SF=1; SD=1; SE=1; SM=1; SW=0;
      end
      `S4: begin
         SF=0; SD=0; SE=0; SM=1; SW=0;
      end
      `S5: begin
         SF=1; SD=1; SE=1; SM=0; SW=1;
      end
      `S6: begin
         SF=1; SD=0; SE=0; SM=0; SW=0;
      end
      `S7: begin
         SF=1; SD=1; SE=1; SM=1; SW=1;
      end
      `S8: begin
         SF=0; SD=0; SE=0; SM=1; SW=1;
      end
      `S9: begin
         SF=1; SD=0; SE=0; SM=0; SW=1;
      end
      default: begin
         SF=0; SD=0; SE=0; SM=0; SW=0;
      end
   endcase
end

always @(halt or SF or SD or SE or SM or SW) begin
   if (halt && SW) begin
      stallIF=0; stallID=0; stallEXE=0; stallMEM=0; stallWB=0;
   end
   else begin
      stallIF=SF; stallID=SD; stallEXE=SE; stallMEM=SM; stallWB=SW;
   end
end
endmodule


module SEXE(stallEXE,iWEcond,iWEdmar,iWEomdr,WEcond,WEdmar,WEomdr);

input        stallEXE, iWEcond, iWEdmar, iWEomdr;
output       WEcond, WEdmar, WEomdr;
reg          WEcond, WEdmar, WEomdr;

always @(stallEXE or iWEcond or iWEdmar or iWEomdr) begin
   if (stallEXE) begin
      WEcond=iWEcond; WEdmar=iWEdmar; WEomdr=iWEomdr;
   end
   else begin
      WEcond=0; WEdmar=0; WEomdr=0;
   end
end
endmodule


module SMEM(stallMEM,iWEimdr,iWEmem,WEimdr,WEmem);

input        stallMEM, iWEimdr, iWEmem;
output       WEimdr, WEmem;
reg          WEimdr, WEmem;

always @(stallMEM or iWEimdr or iWEmem) begin
   if (stallMEM) begin
      WEimdr=iWEimdr; WEmem=iWEmem;
   end
   else begin
      WEimdr=0; WEmem=0;
   end
end
endmodule


module SWB(stallWB,iWEregf,WEregf);

input        stallWB, iWEregf;
output       WEregf;
reg          WEregf;

always @(stallWB or iWEregf) begin
   if (stallWB) WEregf=iWEregf;
   else WEregf=0;
end
endmodule


module datapath(CLK, Reset, MuxA1, MuxA2, ALUop, MuxPC, PCop, MuxD, MuxR,
                WEcond, WEbuf1, WEbuf2, WEregf, OEregf, OErb, WEtemp, OEtemp,
                WEPC, WEimar, WEdmar, WEimdr, WEomdr, RAddr1, RAddr2, RAddr3,
                WAddr, Imme16, DataIn, IAddr, DAddr, DataOut, cond);

input[31:0]  DataIn;
input[15:0]  Imme16;
input[4:0]   RAddr1, RAddr2, RAddr3, WAddr;
input[2:0]   ALUop, MuxPC;
input[1:0]   MuxA1, MuxA2, MuxD;
input        CLK, Reset;
input        PCop, MuxR, WEcond, WEbuf1, WEbuf2, WEregf, OEregf, OErb;
input        WEtemp, OEtemp, WEPC, WEimar, WEdmar, WEimdr, WEomdr;
output[31:0] IAddr, DAddr, DataOut;
output       cond;

wire[31:0]   S1, S2, ALUOut, ALUBuf1Out, ALUBuf2Out;
wire[31:0]   Imme32, RFIn, RaOut, RbOut, RcOut;
wire[31:0]   TempOut, PCIn, PCOut, PCMuxOut, ADD1Out, SUB2Out;
wire[31:0]   IMDROut, OMDRIn;
wire         RcondIn;
tri[31:0]    S2BUS;

ALU          Alu1(S1,S2,ALUop,ALUOut,RcondIn);
Mux4         AluMux1(MuxA1,RaOut,ALUBuf1Out,ALUBuf2Out,IMDROut,S1);
Mux4         AluMux2(MuxA2,S2BUS,ALUBuf1Out,ALUBuf2Out,IMDROut,S2);
Reg32_PCK    AluBuf1(CLK,Reset,WEbuf1,ALUOut,ALUBuf1Out);
Reg32_PCK    AluBuf2(CLK,Reset,WEbuf2,ALUBuf1Out,ALUBuf2Out);
Reg1_PCK     RegCond(CLK,Reset,WEcond,RcondIn,cond);

RegFile      RF(CLK,Reset,WEregf,OEregf,RAddr1,RAddr2,RAddr3,WAddr,RFIn,RaOut,
                RbOut,RcOut);
Mux2         RFMux(MuxR,IMDROut,ALUBuf2Out,RFIn);
Tri_Buf32    bout(OErb,RbOut,S2BUS);

SignExtend   SExt(Imme16,Imme32);
Reg32_PCK    Temp(CLK,Reset,WEtemp,Imme32,TempOut);
Tri_Buf32    tout(OEtemp,TempOut,S2BUS);

Reg32_PCK    PC(CLK,Reset,WEPC,PCIn,PCOut);
Mux5         PCMux(MuxPC,RcOut,ALUBuf1Out,ALUBuf2Out,IMDROut,TempOut,PCMuxOut);
Sub2         SUBPC(PCOut,PCMuxOut,SUB2Out);
Add1         ADDPC(PCOut,ADD1Out);
Mux2         PCsource(PCop,ADD1Out,SUB2Out,PCIn);

Reg32_PCK    IMAR(CLK,Reset,WEimar,PCOut,IAddr);
Reg32_PCK    DMAR(CLK,Reset,WEdmar,ALUOut,DAddr);

Reg32_PCK    IMDR(CLK,Reset,WEimdr,DataIn,IMDROut);
Reg32_PCK    OMDR(CLK,Reset,WEomdr,OMDRIn,DataOut);
Mux4         OMDRMux(MuxD,RcOut,ALUBuf1Out,ALUBuf2Out,IMDROut,OMDRIn);

endmodule


module ALU(SA,SB,op,ALUOut,cond);

input[31:0]  SA, SB;
input[2:0]   op;
output[31:0] ALUOut;
output       cond;
reg[31:0]    ALUOut;
reg          cond;

always @(op or SA or SB) begin
   case(op)
      3'b000: begin   // 0 PASS SB
         ALUOut=SB;
         cond=0;
      end
      3'b001: begin   // 1 ADD
         ALUOut=SA+SB;
         cond=0;
      end
      3'b010: begin   // 2 SUB
         ALUOut=SA-SB;
         cond=0;
      end
      3'b011: begin   // 3 SET IF A<B
         ALUOut=0;
         if (SA<SB) cond=1;
         else cond=0;
      end
      3'b100: begin   // 4 SET IF A>B
         ALUOut=0;
         if (SA>SB) cond=1;
         else cond=0;
      end
      3'b101: begin   // 5 SET IF A<=B
         ALUOut=0;
         if (SA<=SB) cond=1;
         else cond=0;
      end
      3'b110: begin   // 6 SET IF A>=B
         ALUOut=0;
         if (SA>=SB) cond=1;
         else cond=0;
      end
      3'b111: begin   // 7 SET IF A=B
         ALUOut=0;
         if (SA==SB) cond=1;
         else cond=0;
      end
      default: begin
         ALUOut=0;
         cond=0;
      end
   endcase
end
endmodule


module Mux2(select,i0,i1,out);

input[31:0]  i0, i1;
input        select;
output[31:0] out;
reg[31:0]    out;

always @(select or i0 or i1) begin
   case(select)
      1'b0: out=i0;
      1'b1: out=i1;
      default: out=32'b0;
   endcase
end
endmodule


module Mux4(select,i0,i1,i2,i3,out);

input[31:0]  i0, i1, i2, i3;
input[1:0]   select;
output[31:0] out;
reg[31:0]    out;

always @(select or i0 or i1 or i2 or i3) begin
   case(select)
      2'b00: out=i0;
      2'b01: out=i1;
      2'b10: out=i2;
      2'b11: out=i3;
      default: out=32'b0;
   endcase
end
endmodule


module Mux5(select,i0,i1,i2,i3,i4,out);

input[31:0]  i0, i1, i2, i3, i4;
input[2:0]   select;
output[31:0] out;
reg[31:0]    out;

always @(select or i0 or i1 or i2 or i3 or i4) begin
   case(select)
      3'b000: out=i0;
      3'b001: out=i1;
      3'b010: out=i2;
      3'b011: out=i3;
      3'b100: out=i4;
      default: out=32'b0;
   endcase
end
endmodule


module Reg32_PCK(CLK,Reset,WE,DIn,DOut);

input[31:0]  DIn;
input        CLK, Reset, WE;
output[31:0] DOut;
wire[31:0]   DIn;
reg[31:0]    DOut;

always @(posedge CLK) begin
   if (Reset) DOut=0;
   else begin
      if (WE) DOut=DIn;
//      else DOut=DOut;
   end
end
endmodule


module Reg1_PCK(CLK,Reset,WE,DIn,DOut);

input        CLK, Reset, WE, DIn;
output       DOut;
wire         DIn;
reg          DOut;

always @(posedge CLK) begin
   if (Reset) DOut=0;
   else begin
      if (WE) DOut=DIn;
//      else DOut=DOut;
   end
end
endmodule


module Tri_Buf32(Enable,DIn,DOut);

input[31:0]  DIn;
input        Enable;
output[31:0] DOut;
wire[31:0]   DIn;
reg[31:0]    DOut;

always @(Enable or DIn) begin
   if (Enable) DOut=DIn;
   else DOut=32'bz;
end
endmodule


module RegFile(CLK,Reset,WE,OE,RAddr1,RAddr2,RAddr3,WAddr,Rin,Ro1,Ro2,Ro3);

input[31:0]  Rin;
input[4:0]   RAddr1, RAddr2, RAddr3, WAddr;
input        CLK, Reset, WE, OE;
output[31:0] Ro1, Ro2, Ro3;
reg[31:0]    Ro1, Ro2, Ro3;

reg[31:0]    dtemp, Regf[31:0];
reg[4:0]     atemp;

always @(posedge CLK) begin
   if (Reset) begin
      Regf[0]=0;
      Regf[1]=0;
      Regf[2]=0;
      Regf[3]=0;
      Regf[4]=0;
      Regf[5]=0;
      Regf[6]=0;
      Regf[7]=0;
      Regf[8]=0;
      Regf[9]=0;
      Regf[10]=0;
      Regf[11]=0;
      Regf[12]=0;
      Regf[13]=0;
      Regf[14]=0;
      Regf[15]=0;
      Regf[16]=0;
      Regf[17]=0;
      Regf[18]=0;
      Regf[19]=0;
      Regf[20]=0;
      Regf[21]=0;
      Regf[22]=0;
      Regf[23]=0;
      Regf[24]=0;
      Regf[25]=0;
      Regf[26]=0;
      Regf[27]=0;
      Regf[28]=0;
      Regf[29]=0;
      Regf[30]=0;
      Regf[31]=0;
   end
   else if (WE) Regf[WAddr]=Rin;
end

always @(negedge CLK) begin
   if (OE) begin
      Ro1=Regf[RAddr1];
      Ro2=Regf[RAddr2];
      Ro3=Regf[RAddr3];
   end
end
endmodule


module SignExtend(In, Out);

input [15:0]  In;
output[31:0] Out;

assign Out[31]=In[15];
assign Out[30]=In[15];
assign Out[29]=In[15];
assign Out[28]=In[15];
assign Out[27]=In[15];
assign Out[26]=In[15];
assign Out[25]=In[15];
assign Out[24]=In[15];
assign Out[23]=In[15];
assign Out[22]=In[15];
assign Out[21]=In[15];
assign Out[20]=In[15];
assign Out[19]=In[15];
assign Out[18]=In[15];
assign Out[17]=In[15];
assign Out[16]=In[15];
assign Out[15:0]=In[15:0];

endmodule


module Sub2(DIn1,DIn2,DOut);

input[31:0]  DIn1, DIn2;
output[31:0] DOut;
reg[31:0]    DOut;

always @(DIn1 or DIn2) DOut=DIn1+DIn2-2;

endmodule


module Add1(DIn,DOut);

input[31:0]  DIn;
output[31:0] DOut;
reg[31:0]    DOut;

always @(DIn) DOut=DIn+1;

endmodule