Publications
- Book and Book Chapter:
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Programmable logic arrays,''
Encyclopedia of Electrical and Electronics Engineering (John G. Webster, Editor),
John Wiley & Sons, Vol. 17, pp. 334-348, 1999.
- M. Shyu, M.-H. Shieh, Y.-T. Chang, W.-H. Shiue, and Y.-W. Chang,
The Practical Xilinx Designer Lab Book
(translation in Chinese),
Chuan-Hwa Science &
Technology Book Co., 480 pages, Nov. 1998.
- ACM/IEEE Conference Papers:
- K. Zhu, D. F. Wong, and Y.-W. Chang,
``Switch module design with application to two-dimensional segmentation design,''
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pp. 480--485, Santa Clara, CA, Nov. 1993.
- Y.-W. Chang, S. Thakur, K. Zhu, and D. F. Wong,
`` A new global routing algorithm for FPGAs,''
Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pp. 380--385, San Jose, CA, Nov. 1994.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``FPGA global routing based on a new congestion metric,''
Proceedings of IEEE International Conference on Computer Design
(ICCD),
pp. 372--378, Austin, TX, Oct. 1995.
(Received Best Paper Award.)
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Design and analysis of FPGA/FPIC switch modules,''
Proceedings of IEEE International Conference on Computer Design
(ICCD),
pp. 394--401, Austin, TX, Oct. 1995.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch-module design for symmetrical-array-based FPGAs,''
Proceedings of ACM International Symposium on Field Programmable
Gate Arrays (FPGA),
pp. 80--86, Monterey, CA, February 1996.
See an implementation report
for our universal switch modules
from Dept. of EECS, Univ. of California at Berkeley.
- Y.-W. Chang, D. F. Wong, K. Zhu, and C. K. Wong,
``On a new timing-driven routing tree problem,''
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS),
pp. IV: 420--423, Atlanta, GA, May 1996.
- C.-P. Chen, Y.-W. Chang, and D. F. Wong,
``Fast performance-driven optimization for buffered clock
trees based on Lagrangian relaxation,''
Proceedings of 33rd ACM/IEEE Design Automation Conference (DAC),
pp. 405--408, Las Vegas, NV, June 1996.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability,''
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS),
Hong Kong, June 1997.
- G.-M. Wu and Y.-W. Chang,
"Switch-matrix design and routing for FPDs,"
Proceedings of ACM International Symposium on Physical Design
(ISPD),
pp. 158-163, Monterey, CA, April 1998.
- G.-M. Wu and Y.-W. Chang,
"Maximally routable switch matrices for FPD design,"
Proceedings of IEEE International Symposium on Circuits
and Systems (ISCAS-98),
Monterey, CA, May 1998.
- K. Zhu, Y.-W. Chang, and D. F. Wong,
"Timing-driven routing for symmetrical-array-based FPGAs,"
Proceedings of IEEE International Conference on
Computer Design (ICCD-98),
Austin, TX, October 1998.
- Y.-W. Chang, J.-M. Lin, and D. F. Wong,
"Graph matching-based algorithms for FPGA segmentation design,"
Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-98),
pp. 34-39, Santa Clara, Nov. 1998.
- G.-M. Wu, M. Shyu, and Y.-W. Chang,
``Universal switch blocks for three-dimensional FPGA design,''
presented at 1999 ACM International Symposium on Field Programmable
Gate Arrays (FPGA-99) (poster),
Monterey, CA, February 1999.
This work was cited by the article
FPGA'99: Advanced processes unleash architectural ideas
in the EE Times weekly,
February 23, 1999.
- H.-R. Jiang, J.-Y. Jou, and Y.-W. Chang,
``Noise-constrained performance optimization by gate and wire sizing
based on Lagrangian relaxation,''
in Proc. of ACM/IEEE Design Automation Conference (DAC-99),
pp. 90-95, New Orleans, LA, June 1999.
- M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
``Generic universal switch-block architectures and their interactions
with routing,''
in Proc. of IEEE International Conference on Computer Design (ICCD-99), pp. 311-314,
Austin, TX, Oct. 1999.
- C.-T. M. Chao, G.-M. Wu, H.-R. Jiang, and Y.-W. Chang,
``A clustering and probability based partitioning algorithm for
time-multiplexed FPGAs,"
in Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99),
pp. 364-368, Santa Clara, CA, Nov. 1999.
- H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable crosstalk-driven interconnect optimization,"
in Proc. of ACM International Symposium on Physical Design (ISPD-2000),
pp. 128-133, San Diego, CA, Apr. 2000.
- Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu,
``B*-trees: A New Representation for Non-slicing Floorplans,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2000),
pp. 458-463,
LA, CA, June 2000.
(This work received two Best Paper Nominations among the three reviews.)
- Y.-W. Chang and Y.-T. Chang,
``An architecture-driven metric for simultaneous placement and routing for FPGAs,"
in Proc. of ACM/IEEE Design Automation Conference (DAC-2000),
pp. 567-572, LA, CA, June 2000.
- G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,
``Rectilinear block placement using B*-trees,"
in Proc. of IEEE International Conference on Computer Design (ICCD-00),
pp. 351-356, Austin, TX, Oct. 2000.
- S.-R. Pan and Y.-W. Chang,
``Crosstalk-constrained Performance Optimization by Using Wire Sizing
and Perturbation,"
in Proc. of IEEE International Conference on Computer Design (ICCD-00), pp. 581-584,
Austin, TX, Oct. 2000.
- J.-M. Lin abd Y.-W. Chang,
``TCG: A transitive closure graph based representation for non-slicing floorplans,"
to appear in Proc. of ACM/IEEE Design Automation Conference (DAC-2001),
Las Vegas, NV, June 2001.
- T.-C. Chen and Y.-W. Chang,
``Performance optimization by wire and buffer sizing under the transmission line model,"
to appear in Proc. of IEEE International Conference on Computer Design (ICCD-01),
Austin, TX, Nov. 2001.
- G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,
``Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning
,"
to appear in Proc. of IEEE International Conference on Computer Design (ICCD-01),
Austin, TX, Nov. 2001.
- G.-M. Wu and Y.-W. Chang,
``An Algorithm for Dynamically Reconfigurable FPGA Placement,"
to appear in Proc. of IEEE International Conference on Computer Design (ICCD-01),
Austin, TX, Nov. 2001.
- Other Conference Papers:
- Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
"Can FPD switch matrices be universal?,"
The 8th VLSI Design/CAD Symposium,
pp. 253-256, Nangtou, Taiwan, Aug. 1997.
- Y.-D. Chang, Y.-W. Chang, and M. Shyu,
"Design and analysis of universal switch modules for hierarchical FPGAs,"
in Proceedings of the 9th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1998.
- Y.-W. Chang and J.-M. Lin,
"Channel segmentation design for FPGAs,"
in Proceedings of the 9th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1998.
- J.-M. Lin, S.-R. Pan, and Y.-W. Chang,
``A timing-driven matching-based algorithm for array-based FPGA routing,"
in Proceedings of the 10th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1999.
- H.-R. Jiang, S.-R. Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable crosstalk-driven interconnect optimization in the deep
submicron technology,"
in Proceedings of the 10th VLSI Design/CAD Symposium,
Nangtou, Taiwan, Aug. 1999.
- G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,
``Generic ILP-based approaches for time-multiplexed FPGA partitioning,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- G.-M. Wu and Y.-W. Chang,
``Precedence-constrained placement for dynamically reconfigurable FPGAs,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- S.-R. Pan and Y.-W. Chang,
``Performance optimization by wire/buffer sizing under the transmission
line model,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000.
- C.-Y. Chang, Y.-W. Chang, and I. H.-R. Jiang,
``Simultaneous buffer-insertion/-sizing and wire-sizing formulae
with applications to
interconnect-driven floorplanning,"
in Proceedings of The 11th VLSI Design/CAD Symposium,
Pingdong, Taiwan, Aug. 2000
(received Best Student Paper Award).
- S.-M. Lee, Y.-H. Cherng, and Y.-W. Chang,
``Noise-aware buffer planning for interconnect-driven floorplanning,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- J.-M. Lin, S.-P. Lin, and Y.-W. Chang,
``A P-admissible non-slicing floorplan representation with a
worst-case linear-time packing scheme,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- S.-C. Lee, J.-M. Hsu, and Y.-W. Chang,
``Multilevel large-scale module placement/floorplanning using
B*-trees,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen,
``Inductance modeling for on-chip interconnects,"
in Proceedings of The 12th VLSI Design/CAD Symposium,
Hsinchu, Taiwan, Aug. 2001.
- ACM/IEEE Journal Papers:
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch modules for FPGA design,''
ACM Trans. on Design Automation of Electronic Systems (TODAES),
Vol. 1, No. 1, pp. 80--101, January 1996.
See an implementation report
for our universal switch modules
from Dept. of EECS, Univ. of California at Berkeley.
- S. Thakur, Y.-W. Chang, D. F. Wong, and S. Muthukrishnan,
``Algorithms for an FPGA switch module routing problem
with application to global routing,''
IEEE Trans. on Computer-Aided Design (TCAD),
Vol. 16, No. 1, pp. 32--47, January 1997.
- G.-M. Wu and Y.-W. Chang,
"Quasi-universal switch matrices for FPD design,"
in
IEEE Trans. on Computers (TC),
Vol. 48, No. 10, pp. 1107-1122, Oct. 1999.
- M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,
"Generic universal switch blocks,"
in
IEEE Trans. on Computers (TC), vol. 49, no. 4,
pp. 348-359, April 2000.
- Y.-W. Chang, K. Zhu, and D. F. Wong,
``Timing-driven routing for symmetrical-array-based FPGAs,''
ACM Trans. on Design Automation of Electronic Systems,
July 2000.
- H.-R. Jiang, Y.-W. Chang, and J.-Y. Jou,
"Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing (PDF format),"
IEEE Trans. on Computer-Aided Design,
Vol. 19, No. 9, pp. 999--1010, September 2000.
- Y.-W. Chang, J.-M. Lin, and D. F. Wong,
"A matching-based algorithm for FPGA channel segmentation design,"
in
IEEE Trans. Computer-Aided Design, Vol. 20, No. 6, June 2001.
- G.-M. Wu, J.-M. Lin, and Y.-W. Chang,
``Generic ILP-based approaches for time-multiplexed FPGA partitioning,"
to appear in
IEEE Trans. Computer-Aided Design, Vol. 20, 2001.
- H. Fang, Y.-L. Wu, and Y.-W. Chang,
"Comments on "Generic universal switch blocks","
to appear in
IEEE Trans. on Computers (TC), vol. 50,
2001.
- Y.-W. Chang, K. Zhu, D. F. Wong, G.-M. Wu, and C. K. Wong,
"Universal switch blocks for three-dimensional FPGA design,"
in revision, IEEE Trans. on VLSI Systems.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability,''
submitted to IEEE Trans. Computer-Aided Design.
- C.-T. M. Chao, G.-M. Wu, and Y.-W. Chang,
``A clustering and probability based partitioning algorithm for
time-multiplexed FPGAs,"
submitted to IEEE Trans. Computer-Aided Design.
- H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,
``Reliable Crosstalk-driven interconnect optimization,"
submitted to
ACM Trans. on Design Automation of Electronic Systems.
- G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,
``Rectilinear block placement using B*-trees,"
submitted to
ACM Trans. on Design Automation of Electronic Systems.
- G.-M. Wu and Y.-W. Chang,
``Precedence-constrained placement for dynamically reconfigurable FPGAs,"
submitted to
ACM Trans. on Design Automation of Electronic Systems.
- Y.-W. Chang and Y.-T. Chang,
"An architecture-driven simultaneous placement and routing for FPGAs,"
submitted to
IEEE Trans. Computer-Aided Design.
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``An optimal algorithm for computing FPGA minimal dominating sets,''
submitted to IEEE Trans. Computer-Aided Design.
- Technical Reports:
- Y.-W. Chang, D. F. Wong, and C. K. Wong,
``Universal switch modules for FPGA design,''
Dept. of Computer Sciences,
University of Texas at Austin,
TR95-27, August 1995.
- Y.-W. Chang, K. Zhu, D. F. Wong, and C. K. Wong,
``Analysis of FPGA/FPIC switch modules,''
Dept. of Computer Sciences,
University of Texas at Austin,
TR96-32, September 1996.
- Dissertation:
- Other Articles:
- Y.-W. Chang, "Ansel Adams--Master of the Straight Photography (in Chinese)," Light & Shadows, No. 6, June 1985.
- Y.-W. Chang, "Introduction to photography (in Chinese)," Light & Shadows, No. 13, April 1987.
- Y.-W. Chang, "Thoughts on the meanings of images (in Chinese)," Light & Shadows, No. 17,
May 1988.